// Cell names have been changed in this file by netl_namemap on Mon Jan  3 04:00:07 UTC 2022
//////////////////////////////////////////////////////////////////////////////
//
//  pcs_raw_aon_cmn.v
//
//  Raw PCS always-on common module
//
//  Original Author: Ameer Youssef
//  Current Owner:   Ameer Youssef
//
//////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Synopsys, Inc.  All rights reserved.
//
// SYNOPSYS CONFIDENTIAL - This is an unpublished, proprietary work of
// Synopsys, Inc., and is fully protected under copyright and trade secret
// laws.  You may not view, use, disclose, copy, or distribute this file or
// any information contained herein except pursuant to a valid written
// license agreement. It may not be used, reproduced, or disclosed to others
// except in accordance with the terms and conditions of that agreement.
//
//////////////////////////////////////////////////////////////////////////////
//
//    Perforce Information
//    $Author: yilin $
//    $File: //dwh/up16/main/dev/pcs_raw/dig/rtl/pcs_raw_aon_cmn.v $
//    $DateTime: 2016/06/28 15:04:07 $
//    $Revision: #33 $
//
//////////////////////////////////////////////////////////////////////////////

`include "dwc_e12mp_phy_x4_ns_pcs_raw_macros.v"

`timescale 1ns/10fs
module dwc_e12mp_phy_x4_ns_pcs_raw_aon_cmn (
input  wire        phy_reset,
input  wire        phy_func_reset,
output wire        pma_reset,

input  wire        ref_clk_en,
output wire        pma_ref_clk_en,
output wire        ref_clk_req,
output wire        isolate_en,
output wire        isolate_ref_dig_clk,
output wire        isolate_rx_los,

// Mantis 6776 - Keep ref_clk enabled when mplla/b_force_en is asserted
input  wire        mplla_force_en,
input  wire        mpllb_force_en,

`ifdef DWC_E12MP_X4NS_SRAM_SUPPORT
input  wire        sram_bypass,
output wire        sram_init_done,     // top-level output and to power-gated domain
input  wire        sram_init_done_out, // from power-gated domain
input  wire        sram_ext_ld_done,
`endif

input  wire        jtag_tck,
input  wire        cr_para_clk,
input  wire        ref_dig_clk,
input  wire [2:0]  ref_range,

output wire        jtag_clk,
output wire        jtag_clk_n,
output wire        cr_ext_clk,
output wire        cr_ext_clk_rst,
output wire        cr_clk,
output wire        cr_rst_aon,
output wire        cr_rst,
output wire        cr_lane_rst,
output wire        phy_ref_dig_clk,

input  wire        cr_para_sel,
output wire        cr_para_sel_i,

input  wire        lanes_disable,
input  wire        pg_mode_en,
input  wire        pg_reset,
input  wire        pcs_pwr_stable,
input  wire        pma_pwr_stable,
output wire        pcs_pwr_en,
output wire        pma_pwr_en,
output wire        bg_en,

// CREG bus
input  wire [15:0] cr_wr_data,
input  wire        cr_wr_en,
input  wire [31:0] cr_cmn_aon_sel,
output wire [15:0] cr_cmn_aon_rd_data,

// Mantis 7445 - Override pg_mode_en with bs_ce
input  wire        bs_ce,

// Scan signals
input  wire        scan_cr_clk,
input  wire        scan_ref_dig_clk,
input  wire        scan_mode,              
input  wire        scan_shift_cg,
input  wire        scan_set_rst
);

wire        cr_jtag_clk;
wire        cr_ext_clk_in;
wire        cr_ext_clk_rst_aon;
wire        cr_clk_sel_int;
wire        cr_clk_sel_pre;
wire        cr_clk_sel;
wire        cr_clk_mux;
wire        ref_dig_clk_s;
wire        ref_dig_rst;
wire        ref_dig_rst2;
reg         ref_raw_clk_en;
wire        ref_clk_en_sync;
wire        ref_raw_clk;
wire        ref_raw_rst;
wire        ref_clk_en_int_sync_ref_raw_clk;
wire        pg_mode_en_int;
wire        pwr_stable_int;
wire        pwr_stable;
wire        ref_clk_disable;
wire        pg_reset_i;
wire        phy_reset_i;
wire        phy_func_reset_i;

// CREG signals
wire        sram_pgate_bl_en_r;

`ifdef DWC_E12MP_X4NS_SRAM_SUPPORT
wire        sram_ext_ld_en;
wire        pg_reset_sram;
wire        sram_init_done_rst;
wire        sram_init_done_rising;
reg         sram_init_done_out_r;
reg [3:0]   sram_init_done_reg;
`endif

// Mantis 6776 - Keep ref_clk enabled when mplla/b_force_en is asserted
wire        mpll_force_en;
wire        ref_clk_en_int;

`ifdef DWC_E12MP_X4NS_BG_EN_CTL
// assert bandgap if all lane disables (tx and rx) are asserted
// Mantis 7018 - bg_en needs to be kept asserted if refclk_en is asserted. 
assign bg_en = ~(
                 `ifdef DWC_E12MP_X4NS_BG_EN_CTL_PG_MODE_ONLY
                 pg_mode_en_int &
                 `endif
                 lanes_disable & ~pma_ref_clk_en);
`else
// Always assert bandgap
assign bg_en = 1'b1;
`endif

// ---------------------------------------------------
// Mantis 6776 - Keep ref_clk enabled when mplla/b_force_en is asserted
// ---------------------------------------------------
dwc_e12mp_phy_x4_ns_pcs_raw_gen_clk_or2 mpll_a_or_b_force_en (
  .out  (mpll_force_en), 
  .clk1 (mplla_force_en), 
  .clk2 (mpllb_force_en)
);

dwc_e12mp_phy_x4_ns_pcs_raw_gen_clk_or2 ref_clk_en_or_force_en (
  .out  (ref_clk_en_int), 
  .clk1 (mpll_force_en), 
  .clk2 (ref_clk_en)
);

// ---------------------------------------------------
// Generate jtag_clk, jtag_ckl_n and cr_jtag_clk
// ---------------------------------------------------
// Create a positive and negative jtag clocks to deal with falling-edge flops
//
assign jtag_clk = jtag_tck;
//assign jtag_clk_n = ~jtag_tck;
dwc_e12mp_phy_x4_ns_gen_clk_mux jtag_clk_n_mux(
  .out (jtag_clk_n),
  .sel (scan_mode),
  .d0  (~jtag_tck),
  .d1  (jtag_tck)
);

// CREG clock
assign cr_jtag_clk = jtag_clk_n;
    
// ---------------------------------------------------
// Generate cr_ext_clk
// ---------------------------------------------------
// Mux jtag/cr_para clocks
dwc_e12mp_phy_x4_ns_gen_mux cr_para_sel_mux (
  .out (cr_para_sel_i),
  .sel (scan_mode),
  .d0  (cr_para_sel),
  .d1  (1'b0)
);
    
// Mux jtag/cr_para clocks
dwc_e12mp_phy_x4_ns_gen_clk_mux jtag_creg_clk_mux (
  .out (cr_ext_clk_in),
  .sel (cr_para_sel_i),
  .d0  (cr_jtag_clk),
  .d1  (cr_para_clk)
);
    
// Zero-out cr_ext_clk during phy_reset
// If input cr_ext_clk is initially stopped high, then this will lock up the
// GLCM with ref_raw_clk, so force internally to zero during phy_reset
// Reset sync on cr_ext_clk should take care of glitches when phy_reset is removed
dwc_e12mp_phy_x4_ns_gen_clk_mux cr_ext_clk_mux (
  .out (cr_ext_clk),
  .sel (phy_reset & ~scan_mode),
  .d0  (cr_ext_clk_in),
  .d1  (1'b0)
);

// Mantis 6720
// Generate a synchronous reset on cr_ext_clk based om
// phy_reset or ref_clk_en - this is used to reset
// the GLCM in the event that the cr_ext_clk is not
// active
dwc_e12mp_phy_x4_ns_pcs_raw_gen_rst_sync cr_ext_clk_rst_aon_sync (
  .sync_rst       (cr_ext_clk_rst_aon),
  .clk            (cr_ext_clk),
  .async_rst      (phy_reset | cr_clk_sel),
  .scan_mode_i    (scan_mode),
  .scan_set_rst_i (scan_set_rst)
);

// ---------------------------------------------------
// Generate ref_raw_clk
// ---------------------------------------------------
// Mux ref_dig_clk with scan_ref_dig_clk
dwc_e12mp_phy_x4_ns_gen_clk_mux ref_dig_clk_scan_mux (
  .out (ref_dig_clk_s),
  .sel (scan_mode),
  .d0  (ref_dig_clk),
  .d1  (scan_ref_dig_clk)
);

// divide down ref_dig_clk_s if ref_range[2] is asserted
dwc_e12mp_phy_x4_ns_pcs_raw_gen_rst_sync ref_dig_rst_sync (
  .sync_rst        (ref_dig_rst),
  .clk             (ref_dig_clk_s),
  .async_rst       (!pma_ref_clk_en | phy_reset),
  .scan_mode_i     (scan_mode),
  .scan_set_rst_i  (scan_set_rst)
);

always @(posedge ref_dig_clk_s or posedge ref_dig_rst) begin
  if (ref_dig_rst)
    ref_raw_clk_en <= 1'b1;
  else
    ref_raw_clk_en <= ~ref_range[2] | ~ref_raw_clk_en;
end

// Need to have phy_ref_dig_clk toggling during a phy_reset
// so cannot use phy_reset to reset the clk_gate
dwc_e12mp_phy_x4_ns_pcs_raw_gen_rst_sync ref_dig_rst2_sync (
  .sync_rst        (ref_dig_rst2),
  .clk             (ref_dig_clk_s),
  .async_rst       (!pma_ref_clk_en),
  .scan_mode_i     (scan_mode),
  .scan_set_rst_i  (scan_set_rst)
);

dwc_e12mp_phy_x4_ns_gen_clk_gate ref_raw_clk_gate(
  .en_clk          (ref_raw_clk),
  .clk             (ref_dig_clk_s),
  .rst             (ref_dig_rst2),
  .en              (ref_raw_clk_en),
  .scan_mode_i     (scan_mode),
  .scan_shift_cg_i (scan_shift_cg),
  .scan_set_rst_i  (scan_set_rst)
);

// Generate a synchronous reset on ref_raw_clk
// Mantis 6810 - For async resets that already have scan_rst muxed
// onto them, AND them with ~scan_mode to prevent C26 DFT violations
// on the atpg_cov flop within the gen_rst_sync.
wire ref_dig_rst2_async;
dwc_e12mp_phy_x4_ns_gen_clk_and2 ref_dig_rst2_scan_and (
  .out (ref_dig_rst2_async), 
  .clk (ref_dig_rst2), 
  .en  (~scan_mode)
);

dwc_e12mp_phy_x4_ns_pcs_raw_gen_rst_sync #(.ATPG_COV(0)) ref_raw_rst_sync (
  .sync_rst       (ref_raw_rst),
  .clk            (ref_raw_clk),
  .async_rst      (ref_dig_rst2_async),
  .scan_mode_i    (scan_mode),
  .scan_set_rst_i (scan_set_rst)
);

// ---------------------------------------------------
// Disable PG mode during scan
// ---------------------------------------------------
dwc_e12mp_phy_x4_ns_gen_mux pg_mode_en_mux (
  .out (pg_mode_en_int),
  .sel (scan_mode | bs_ce),
  .d0  (pg_mode_en),
  .d1  (1'b0)
);
    
// ---------------------------------------------------
// Generate cr_clk
// ---------------------------------------------------
// Synchronize the ref_clk_en signal to the ref_raw_clk domain
// Reset the syncronizer asychronously to 0 when ref_clk_en
// is de-asserted using the ref_raw_rst signal
dwc_e12mp_phy_x4_ns_gen_sync sync_ref_clk_en_ref_dig_clk (
  .q   (ref_clk_en_int_sync_ref_raw_clk),
  .clk (ref_raw_clk),
  .rst (ref_raw_rst),
  .d   (ref_clk_en_int)
);

assign cr_clk_sel_int = ref_clk_en_int_sync_ref_raw_clk;

// Select source for cr_clk (ref_dig_clk or cr_ext_clk)
// Note: when pg_mode_en_int=1, then always select ref_dig_clk
//       since we will isolate the PHY when ref_clk_en deasserts
//       (also if cr_ext_clk is selected but not running then we'd never isolate)
dwc_e12mp_phy_x4_ns_gen_mux cr_clk_sel_mux (
  .out (cr_clk_sel_pre),
  .sel (pg_mode_en_int),
  .d0  (cr_clk_sel_int),
  .d1  (1'b1)
);

`ifdef DWC_FPGA_MODE
 assign cr_clk_mux = ref_raw_clk;
`else
`ifdef DWC_E12MP_X4NS_SRAM_SUPPORT
// Mantis 7174 - Use cr_clk for sram_clk
// Use sram_init_done_out (input from power-gated domain) to switch
// the GLCM.  Then flop this signal for outputting
assign sram_ext_ld_en = ~sram_bypass & sram_init_done_out & ~sram_ext_ld_done;
assign cr_clk_sel = cr_clk_sel_pre & ~sram_ext_ld_en;
`else
assign cr_clk_sel = cr_clk_sel_pre;
`endif
// GLCM between cr_ext_clk with ref_raw_clk clock 
// Setup GLCM to output ref_raw_clk during reset
dwc_e12mp_phy_x4_ns_pcs_raw_gen_glcm cr_clk_glcm (
 .clk_out         (cr_clk_mux),
 .clk_a_en_out    (),
 .clk_b_en_out    (),
`ifdef DWC_E12MP_X4NS_SRAM_SUPPORT
 .clk_sel         (cr_clk_sel & ~sram_ext_ld_en),
`else
 .clk_sel         (cr_clk_sel),
`endif
 .clk_a           (cr_ext_clk),
 .clk_b           (ref_raw_clk),
 .rst_a           (cr_ext_clk_rst_aon),
 .rst_b           (ref_raw_rst),
 .scan_mode_i     (scan_mode),
 .scan_shift_cg_i (scan_shift_cg),
 .scan_set_rst_i  (scan_set_rst)
);
`endif

// Mux in scan_clk with CR clock 
dwc_e12mp_phy_x4_ns_gen_clk_mux creg_clk_scan_mux (
  .out (cr_clk),
  .sel (scan_mode),
  .d0  (cr_clk_mux),
  .d1  (scan_cr_clk)
);

// Generate a synchronous reset on cr_clk
dwc_e12mp_phy_x4_ns_pcs_raw_gen_rst_sync cr_rst_aon_sync (
  .sync_rst       (cr_rst_aon),
  .clk            (cr_clk),
  .async_rst      (phy_reset),
  .scan_mode_i    (scan_mode),
  .scan_set_rst_i (scan_set_rst)
);

// ---------------------------------------------------
// Generate phy_ref_dig_clk
// ---------------------------------------------------
// sync clock enable
dwc_e12mp_phy_x4_ns_gen_sync #(.RST_VAL(1)) sync_ref_clk_en (
  .q   (ref_clk_en_sync),
  .clk (cr_clk),
  .rst (cr_rst_aon),
  .d   (ref_clk_en_int)
);
  
// clock gate
// Need to have phy_ref_dig_clk toggling during a phy_reset
// so cannot use phy_reset to reset the clk_gate
// Mantis 7205 - Use ref_raw_clk as source of phy_ref_dig_clk
dwc_e12mp_phy_x4_ns_gen_clk_gate cr_clk_gate (
  .en_clk          (phy_ref_dig_clk),
  .clk             (ref_raw_clk),
  .rst             (ref_raw_rst),
  .en              (ref_clk_en_int_sync_ref_raw_clk),
  .scan_mode_i     (scan_mode),
  .scan_shift_cg_i (scan_shift_cg),
  .scan_set_rst_i  (scan_set_rst)
);

// ------------------------------------------------------------
// Generate isolate_en and
//          isolate_ref_dig_clk, pma_ref_clk_en, ref_clk_req
// ------------------------------------------------------------
reg [3:0] ref_clk_en_sync_d;
always @(posedge cr_clk or posedge cr_rst_aon) begin
  if (cr_rst_aon)
    ref_clk_en_sync_d <= 4'h0;
  else
    ref_clk_en_sync_d <= {ref_clk_en_sync_d[2:0],ref_clk_en_sync};
end

// isolate Raw PCS after a 2 cycles (from ref_clk_en deassertion)
// and remove isolation immediately
dwc_e12mp_phy_x4_ns_gen_clk_and3 isolate_en_and (
  .out (isolate_en), 
  .clk (~ref_clk_en_sync_d[1]), 
  .en1 (~ref_clk_en_int),
  .en2 (pg_mode_en_int)
);

// Mantis 7050 - Add a falling-edge flop on the output of
// ref_clk_en_sync_d[3] to disable/isolate the clock on 
// the falling edge.  This will prevent combinational loops.
// First create an inverted clock for the new flop.  This
// clock will be inverted in functional mode but non-inverted
// in scan mode.
wire cr_clk_n;
dwc_e12mp_phy_x4_ns_gen_mux cr_clk_n_mux (
  .out (cr_clk_n),
  .sel (scan_mode),
  .d0  (~cr_clk),
  .d1  (cr_clk)
);

reg ref_clk_en_n;
always @(posedge cr_clk_n or posedge cr_rst_aon) begin
   if (cr_rst_aon)
      ref_clk_en_n <= 1'b0;
   else
      ref_clk_en_n <= ref_clk_en_sync_d[3];
end

// isolate ref_dig_clk after a 4 cycles (from ref_clk_en deassertion)
// and remove isolation immediately
dwc_e12mp_phy_x4_ns_gen_clk_and2 ref_clk_disable_and (
  .out (ref_clk_disable), 
  .clk (~ref_clk_en_n), 
  .en  (~ref_clk_en_int)
);
dwc_e12mp_phy_x4_ns_gen_clk_and2 ref_clk_dis_and (
  .out (isolate_ref_dig_clk), 
  .clk (pg_mode_en_int), 
  .en  (ref_clk_disable)
);

// Mantis 7051 - Create separate isolation signal for rx_los
assign isolate_rx_los = ~pwr_stable_int;


//assign pma_ref_clk_en = ~ref_clk_disable;
//assign ref_clk_req    = ~ref_clk_disable;
// We should not stage the turning off of the refclk
// when power-gating is disabled (Mantis 6363)
dwc_e12mp_phy_x4_ns_gen_mux pma_ref_clk_en_mux (
  .out (pma_ref_clk_en),
  .sel (pg_mode_en_int),
  .d0  (ref_clk_en_int),
  .d1  (~ref_clk_disable)
);
dwc_e12mp_phy_x4_ns_gen_mux ref_clk_req_mux (
  .out (ref_clk_req),
  .sel (pg_mode_en_int),
  .d0  (ref_clk_en_int),
  .d1  (~ref_clk_disable)

);

// ---------------------------------------------------------------
// Generate pcs_pwr_en and pma_pwr_en outputs
// ---------------------------------------------------------------
dwc_e12mp_phy_x4_ns_gen_mux pma_pwr_en_mux (
  .out (pma_pwr_en),
  .sel (pg_mode_en_int),
  .d0  (1'b1),
  .d1  (~pg_reset)
);
dwc_e12mp_phy_x4_ns_gen_mux pcs_pwr_en_mux (
  .out (pcs_pwr_en),
  .sel (pg_mode_en_int),
  .d0  (1'b1),
  .d1  (~pg_reset)
);

// ---------------------------------------------------------------
// Generate pg_reset_i
//    - asserted when pg_reset is high or power is not stable
//    - deasserted when ref_dig_clk is back
// ---------------------------------------------------------------
//assign pwr_stable = pcs_pwr_stable & pma_pwr_stable & ~pg_reset;
dwc_e12mp_phy_x4_ns_gen_clk_and3 pwr_stable_and (
  .out (pwr_stable),
  .clk (pcs_pwr_stable),
  .en1 (pma_pwr_stable),
  .en2 (~pg_reset)
);

// Mantis 7042 - Tie pwr_stable to 1'b1 when pg_mode is not enabled
dwc_e12mp_phy_x4_ns_gen_mux pwr_stable_mux (
  .out (pwr_stable_int),
  .sel (pg_mode_en_int),
  .d0  (1'b1),
  .d1  (pwr_stable)
);

dwc_e12mp_phy_x4_ns_pcs_raw_gen_rst_sync pg_reset_i_rst_sync (
  .sync_rst       (pg_reset_i),
  .clk            (ref_dig_clk_s),
  .async_rst      (~pwr_stable_int | phy_reset),
  .scan_mode_i    (scan_mode),
  .scan_set_rst_i (scan_set_rst)
);

//assign phy_reset_i = pg_mode_en ? pg_reset_i : phy_reset;
dwc_e12mp_phy_x4_ns_gen_mux phy_reset_i_mux (
  .out (phy_reset_i),
  .sel (pg_mode_en_int),
  .d0  (phy_reset),
  .d1  (pg_reset_i)
);

// ---------------------------------------------------------------
// Generate resets for power-gated domains:
//       pma_reset, cr_ext_clk_rst, cr_rst and cr_lane_rst
// ---------------------------------------------------------------

// Functional reset comes from a register in power-gated domain
// so only use it if isolation is disabled.
dwc_e12mp_phy_x4_ns_gen_clk_and2 phy_func_reset_and (
  .out (phy_func_reset_i),
  .clk (phy_func_reset),
  .en  (~isolate_en)
);

assign pma_reset = phy_reset_i | phy_func_reset_i;

// Generate a synchronous reset on cr_ext_clk
dwc_e12mp_phy_x4_ns_pcs_raw_gen_rst_sync cr_ext_clk_rst_sync (
  .sync_rst       (cr_ext_clk_rst),
  .clk            (cr_ext_clk),
  .async_rst      (phy_reset_i),
  .scan_mode_i    (scan_mode),
  .scan_set_rst_i (scan_set_rst)
);

// Generate a synchronous reset on cr_clk
dwc_e12mp_phy_x4_ns_pcs_raw_gen_rst_sync cr_rst_sync (
  .sync_rst       (cr_rst),
  .clk            (cr_clk),
  .async_rst      (phy_reset_i),
  .scan_mode_i    (scan_mode),
  .scan_set_rst_i (scan_set_rst)
);

// Generate a synchronous cr_lane_rst on cr_clk
// Mantis 6810 - For async resets that already have scan_rst muxed
// onto them, AND them with ~scan_mode to prevent C26 DFT violations
// on the atpg_cov flop within the gen_rst_sync.
wire cr_rst_async;
dwc_e12mp_phy_x4_ns_gen_clk_and2 cr_rst_scan_and (
  .out (cr_rst_async), 
  .clk (cr_rst), 
  .en  (~scan_mode)
);

dwc_e12mp_phy_x4_ns_pcs_raw_gen_rst_sync #(.ATPG_COV(0)) cr_lane_rst_sync (
  .sync_rst       (cr_lane_rst),
  .clk            (cr_clk),
  .async_rst      (cr_rst_async | phy_func_reset_i),
  .scan_mode_i    (scan_mode),
  .scan_set_rst_i (scan_set_rst)
);

`ifdef DWC_E12MP_X4NS_SRAM_SUPPORT
// Store the value of sram_init_done in an always-on register
// so that the SRAM bootloader doesn't automaticaly kick-off
// on power gated exit.  This register can be selectively
// reset to also force the bootloader to kick-off on power
// gated exit

dwc_e12mp_phy_x4_ns_gen_clk_and2 pg_reset_sram_and (
  .out (pg_reset_sram), 
  .clk (pg_reset_i), 
  .en  (sram_pgate_bl_en_r)
);

// Synchronize reset to cr_clk
dwc_e12mp_phy_x4_ns_pcs_raw_gen_rst_sync #(.ATPG_COV(0)) pg_reset_sram_sync (
  .sync_rst       (sram_init_done_rst),
  .clk            (cr_clk),
  .async_rst      (pg_reset_sram | phy_reset),
  .scan_mode_i    (scan_mode),
  .scan_set_rst_i (scan_set_rst)
);


// Generate a pulse on the rising edge of sram_init_done_out
// coming from the power-gated domain
assign sram_init_done_rising = sram_init_done_out & ~sram_init_done_out_r;

always @(posedge cr_clk or posedge cr_rst_aon) begin
   if (cr_rst_aon) begin
      sram_init_done_out_r <= 1'b0;
   end else begin
      sram_init_done_out_r <= sram_init_done_out;
   end
end

always @(posedge cr_clk or posedge sram_init_done_rst) begin
   if (sram_init_done_rst) begin
      sram_init_done_reg[3:0]  <= 4'd0;
   end else begin
      if (sram_init_done_rising) begin
         sram_init_done_reg[0] <= 1'b1;
      end
      sram_init_done_reg[3:1] <= sram_init_done_reg[2:0];
   end
end

assign sram_init_done = sram_init_done_reg[3];

`endif

// ---------------------------------------------------------------------
// %%CREG SRAM_PGATE_BL_EN - Enable SRAM bootloader on power-gated exit
//   OFFSET: 0x00
//   ATTR: READ,WRITE
//   FIELDS:
//      [0] SRAM_PGATE_BL_EN - Enable SRAM bootloader on power-gated exit.
//          RESET: 0x0
//
// ---------------------------------------------------------------------
wire [15:0] cr_sram_pgate_bl_en_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(1), .RST_VAL(1'b0), .MSK_VAL(1'b0)) 
 sram_pgate_bl_en_reg (
  .cr_val      ({
                 sram_pgate_bl_en_r
                 }),
  .cr_rd_data  (cr_sram_pgate_bl_en_rd_data),
  .cr_wr_data  (cr_wr_data),
  .cr_wr_en    (cr_wr_en),
  .cr_clk      (cr_clk),
  .cr_rst      (cr_rst_aon),
  .cr_sel      (cr_cmn_aon_sel[0]),
  .cr_self_clr (1'b0)
);

// Muxed register read for AON CMN registers
//     
assign cr_cmn_aon_rd_data = cr_sram_pgate_bl_en_rd_data;

 
endmodule
